Instruction decoder

The instruction decoder is reponsible for mapping a machine instruction together with the t-state counter to the control lines. The instruction decoder in the SAM-SMD uses two SST39SF010 EEPROMS for this mapping. One of the EEPROMS directs 8 parallel control lines, which are lines that can be pulled high or low in any particular combination. The second EEPROM is tied to four 74HC238 which control 2 x 15 orthogonal control lines. Orthogonal control lines are such that only one of the 15 lines can be activated at one time. This limitation comes with the benefit that a single chip can control far more control lines, here 30 instead of 8. Note that the 2 x 15 orthogonal control lines form two sets, i.e. any control line in one set can be activated together with any other control line in the other set. The only limitation is thus that within a set, no two control lines can be activated simultaneously.

Mapping

Note

In the tables below, we use the following abbreviations: * ALU: Arithmetic and Logic Unit * IR: Instrucion Register * MAR: Memory Address Register * PC: Program Counter

Table 1 Parallel Control Lines

Control line	Micro-instruction	Description
PCL0	CE	PC count enable
PCL1	FI	ALU flag register in
PCL2	SU	ALU subtract operation
PCL3	X	Unused
PCL4	X	Unused
PCL5	X	Unused
PCL6	HLT	Halts the clock line
PCL7	/MR	Used internally to reset T-state counter

Table 2 Orthogonal Control Lines A

Control line	Micro-instruction	Description
OCA1	MI	MAR in: Retrieves memory address from data bus
OCA2	II	IR in: Retrieves instruction from data bus
OCA3	J	PC jump: Retrieves address from data bus
OCA4	AI	A-register in: Stores value from data bus
OCA5	BI	B-register in: Stores value from data bus
OCA6	OI	Output register in: Retrieves value from data bus
OCA7	RI	RAM in: Stores value from data bus in memory
OCA8	TI	T-register in: Stores value from data bus
OCA9	X	Unused
OCA10	X	Unused
OCA11	X	Unused
OCA12	X	Unused
OCA13	X	Unused
OCA14	X	Unused
OCA15	X	Unused

Table 3 Orthogonal Control Lines B

Control line	Micro-instruction	Description
OCB1	CO	PC counter out: Asserts current PC value on data bus
OCB2	RRO	ROM out: Asserts ROM value onto data bus
OCB3	AO	A-register out: Asserts register value onto data bus
OCB4	BO	B-register out: Asserts register value onto data bus
OCB5	EO	ALU sum out: Asserts result of summation onto data bus
OCB6	RO	RAM out: Asserts RAM value onto data bus
OCB7	TO	T-register: Asserts register value onto data bus
OCB8	CODE008	Description for control line 8.
OCB9	CODE009	Description for control line 9.
OCB10	CODE010	Description for control line 10.
OCB11	CODE011	Description for control line 11.
OCB12	CODE012	Description for control line 12.
OCB13	CODE013	Description for control line 13.
OCB14	CODE014	Description for control line 14.
OCB15	CODE015	Description for control line 15.