VERA Module
Overview
Origins and Continuation
The original design
Project timeline
Compatibility
The VERA Ecosystem
FPGA firmware
Programmer and command-line tool
Arduino Mega bridge
VERA Test Console
Hardware Configurations
Full audio-jack board
Mini audio-jack board
Common architecture
Integration
Connecting a Host
Parallel interface
Read and write cycles
Memory-mapped or port-mapped
Interrupt handling
Bring-up sequence
Register Reference
Quick map
VRAM pointers and data ports
Control register
Interrupt enable
Interrupt status
Display-controller banks
Bank 0: output and scaling
Bank 1: active area
Banks 60-63: ecosystem identifier
Layer registers
PCM audio registers
SPI registers
Working with VRAM
Address-space layout
Setting a pointer
Sequential transfers
Two-port patterns
Alignment and allocation
Programming
Graphics Programming
Composition order
Display setup
Palette format
Layer modes
Tile mode
Bitmap mode
Sprites
Collision groups
A dependable first image
Audio and Storage
Programmable sound generator
PCM playback
SPI controller
VERA Test Console
Install and connect
Test progression
Troubleshooting
Bridge wiring
Project
Sources and Scope
Primary material
Historical cross-checks
Documentation policy
VERA Module
Index
Index